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cyiv-53001-1.8 ? 2013 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. cyclone iv device handbook, volume 3 december 2013 feedback subscribe iso 9001:2008 registered 1. cyclone iv device datasheet this chapter describes the electrical an d switching characteristics for cyclone ? iv devices. electrical characteristics in clude operating conditions and power consumption. switching characteristics include transceiver specifications, core, and periphery performance. this chapter also describes i/o timing, including programmable i/o element (ioe) delay and programmable output buffer delay. this chapter includes the following sections: ?operating conditions? on page 1?1 ?power consumption? on page 1?16 ?switching characteristics? on page 1?16 ?i/o timing? on page 1?37 ?glossary? on page 1?37 operating conditions when cyclone iv devices are implemented in a system, they are rated according to a set of defined parameters. to maintain the highest possible performance and reliability of cyclone iv devices, you must consider the operating requirements described in this chapter. cyclone iv devices are offered in commercial, industrial, extended industrial and, automotive grades. cyclone iv e devices offe r ?6 (fastest), ?7, ?8, ?8l, and ?9l speed grades for commercial devices, ?8l speed gr ades for industrial devices, and ?7 speed grade for extended industrial and automotive devices. cyclone iv gx devices offer ?6 (fastest), ?7, and ?8 speed grades for commercial devices and ?7 speed grade for industrial devices. f for more information about the supported speed grades for respective cyclone iv devices, refer to the cyclone iv fpga device family overview chapter. 1 cyclone iv e devices are offered in core voltages of 1.0 and 1.2 v. cyclone iv e devices with a core voltage of 1.0 v have an ?l? prefix attached to the speed grade. in this chapter, a prefix associated with th e operating temperature range is attached to the speed grades; commercial with a ?c? pr efix, industrial with an ?i? prefix, and automotive with an ?a? prefix. therefore, commercial devices are indicated as c6, c7, c8, c8l, or c9l per respective speed grade. industrial devices are indicated as i7, i8, or i8l. automotive devi ces are indicated as a7. december 2013 cyiv-53001-1.8
1?2 chapter 1: cyclone iv device datasheet operating conditions cyclone iv device handbook, december 2013 altera corporation volume 3 1 cyclone iv e industrial devices i7 are offe red with extended operating temperature range. absolute maximum ratings absolute maximum ratings define the maxi mum operating conditions for cyclone iv devices. the values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied at these conditions. table 1?1 lists the absolute maximum ratings for cyclone iv devices. c conditions beyond those listed in table 1?1 cause permanent damage to the device. additionally, device operation at the abso lute maximum ratings for extended periods of time have adverse effects on the device. maximum allowed overshoot or undershoot voltage during transitions, input signals may overshoot to the voltage shown in table 1?2 and undershoot to ?2.0 v for a magnitude of currents less than 100 ma and for periods shorter than 20 ns. table 1?2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device. the maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. table 1?1. absolute maximum ratings for cyclone iv devices (1) symbol parameter min max unit v ccint core voltage, pci express ? (pcie ? ) hard ip block, and transceiver physical coding sublayer (pcs) power supply ?0.5 1.8 v v cca phase - locked loop (pll) analog power supply ?0.5 3.75 v v ccd_pll pll digital power supply ?0.5 4.5 v v ccio i/o banks power supply ?0.5 3.75 v v cc_clkin differential clock input pins power supply ?0.5 4.5 v v cch_gxb transceiver output buffer power supply ?0.5 3.75 v v cca_gxb transceiver physical medium attachment (pma) and auxiliary power supply ?0.5 3.75 v v ccl_gxb transceiver pma and auxiliary power supply ?0.5 1.8 v v i dc input voltage ?0.5 4.2 v i out dc output current, per pin ?25 40 ma t stg storage temperature ?65 150 c t j operating junction temperature ?40 125 c note to table 1?1 : (1) supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the power supply.
chapter 1: cyclone iv device datasheet 1?3 operating conditions december 2013 altera corporation cyclone iv device handbook, volume 3 1 a dc signal is equivalent to 100% duty cycle. for example, a signal that overshoots to 4.3 v can only be at 4.3 v for 65% over the li fetime of the device; for a device lifetime of 10 years, this amounts to 65/10ths of a year. figure 1?1 shows the methodology to determine the overshoot duration. the overshoot voltage is shown in red and is present on the input pin of the cyclone iv device at over 4.3 v but below 4.4 v. from table 1?2 , for an overshoot of 4.3 v, the percentage of high time for the overshoot ca n be as high as 65% over a 10-year period. percentage of high time is calculated as ([delta t]/t) 100. this 10-year period assumes that the device is always turned on with 100% i/o toggle rate and 50% duty cycle signal. for lower i/o toggle rates and situations in which the device is in an idle state, lifetimes are increased. table 1?2. maximum allowed overshoot during transitions over a 10 - year time frame for cyclone iv devices symbol parameter condition (v) overshoot duration as % of high time unit v i ac input voltage v i = 4.20 100 % v i = 4.25 98 % v i = 4.30 65 % v i = 4.35 43 % v i = 4.40 29 % v i = 4.45 20 % v i = 4.50 13 % v i = 4.55 9 % v i = 4.60 6 % figure 1?1. cyclone iv devices overshoot duration 3.3 v 4.3 v 4.4 v t d t
1?4 chapter 1: cyclone iv device datasheet operating conditions cyclone iv device handbook, december 2013 altera corporation volume 3 recommended operating conditions this section lists the functional operation limits for ac and dc parameters for cyclone iv devices. table 1?3 and table 1?4 list the steady-state voltage and current values expected from cyclone iv e and cy clone iv gx devices. all supplies must be strictly monotonic without plateaus. table 1?3. recommended operating conditions for cyclone iv e devices (1) , (2) (part 1 of 2) symbol parameter conditions min typ max unit v ccint (3) supply voltage for internal logic, 1.2-v operation ? 1.15 1.2 1.25 v supply voltage for internal logic, 1.0-v operation ? 0.97 1.0 1.03 v v ccio (3) , (4) supply voltage for output buffers, 3.3-v operation ? 3.135 3.3 3.465 v supply voltage for output buffers, 3.0-v operation ? 2.85 3 3.15 v supply voltage for output buffers, 2.5-v operation ? 2.375 2.5 2.625 v supply voltage for output buffers, 1.8-v operation ? 1.71 1.8 1.89 v supply voltage for output buffers, 1.5-v operation ? 1.425 1.5 1.575 v supply voltage for output buffers, 1.2-v operation ? 1.14 1.2 1.26 v v cca (3) supply (analog) voltage for pll regulator ? 2.375 2.5 2.625 v v ccd_pll (3) supply (digital) voltage for pll, 1.2-v operation ? 1.15 1.2 1.25 v supply (digital) voltage for pll, 1.0-v operation ? 0.97 1.0 1.03 v v i input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j operating junction temperature for commercial use 0 ? 85 c for industrial use ?40 ? 100 c for extended temperature (5) ?40 ? 125 c for automotive use ?40 ? 125 c t ramp power supply ramp time standard power-on reset (por) (6) 50 s ? 50 ms ? fast por (7) 50 s ? 3 ms ?
chapter 1: cyclone iv device datasheet 1?5 operating conditions december 2013 altera corporation cyclone iv device handbook, volume 3 i diode magnitude of dc current across pci-clamp diode when enable ???10ma notes to table 1?3 : (1) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. cyclone iv e 1.2 v core voltage devices only support c6, c7, c8, i7, and a7 speed grades. (2) v ccio for all i/o banks must be powered up during devi ce operation. all vcca pins must be powered to 2.5 v (even when plls are not used) and must be powered up and po wered down at the same time. (3) v cc must rise monotonically. (4) v ccio powers all input buffers. (5) the i7 devices support extended operating junction temperature up to 125c (usual ra nge is ?40c to 100c). when using i7 de vices at the extended junction temperature ranging from ?40c to 125c, select c8 as the target device wh en designing in the quartus ? ii software. the i7 devices meet all c8 timi ng specifications when i7 devices operate beyond 100 c and up to 125c. (6) the por time for standard por ranges between 50 and 200 ms. each individual power supply must reach the recommended operating range within 50 ms. (7) the por time for fast por ranges between 3 and 9 ms. each individual power supply must reach the recomm ended operating range within 3ms. table 1?3. recommended operating conditions for cyclone iv e devices (1) , (2) (part 2 of 2) symbol parameter conditions min typ max unit table 1?4. recommended operating conditions for cyclone iv gx devices (part 1 of 2) symbol parameter conditions min typ max unit v ccint (3) core voltage, pcie hard ip block, and transceiver pcs power supply ? 1.16 1.2 1.24 v v cca (1) , (3) pll analog power supply ? 2.375 2.5 2.625 v v ccd_pll (2) pll digital power supply ? 1.16 1.2 1.24 v v ccio (3) , (4) i/o banks power supply for 3.3 - v operation ? 3.135 3.3 3.465 v i/o banks power supply for 3.0 - v operation ? 2.85 3 3.15 v i/o banks power supply for 2.5 - v operation ? 2.375 2.5 2.625 v i/o banks power supply for 1.8 - v operation ? 1.71 1.8 1.89 v i/o banks power supply for 1.5 - v operation ? 1.425 1.5 1.575 v i/o banks power supply for 1.2 - v operation ? 1.14 1.2 1.26 v v cc_clkin (3) , (5) , (6) differential clock input pins power supply for 3.3 - v operation ? 3.135 3.3 3.465 v differential clock input pins power supply for 3.0 - v operation ? 2.85 3 3.15 v differential clock input pins power supply for 2.5 - v operation ? 2.375 2.5 2.625 v differential clock input pins power supply for 1.8 - v operation ? 1.71 1.8 1.89 v differential clock input pins power supply for 1.5 - v operation ? 1.425 1.5 1.575 v differential clock input pins power supply for 1.2 - v operation ? 1.14 1.2 1.26 v
1?6 chapter 1: cyclone iv device datasheet operating conditions cyclone iv device handbook, december 2013 altera corporation volume 3 esd performance this section lists the electrostatic discha rge (esd) voltages using the human body model (hbm) and charged device model (cdm) for cyclone iv devices general purpose i/os (gpios) and high-speed serial interface (hssi) i/os. table 1?5 lists the esd for cyclone iv devices gpios and hssi i/os. v cch_gxb transceiver output buffer power supply ? 2.375 2.5 2.625 v v cca_gxb transceiver pma and auxiliary power supply ? 2.375 2.5 2.625 v v ccl_gxb transceiver pma and auxiliary power supply ? 1.16 1.2 1.24 v v i dc input voltage ? ?0.5 ? 3.6 v v o dc output voltage ? 0 ? v ccio v t j operating junction temperature for commercial use 0 ? 85 c for industrial use ?40 ? 100 c t ramp power supply ramp time standard power - on reset (por) (7) 50 s ? 50 ms ? fast por (8) 50 s ? 3 ms ? i diode magnitude of dc current across pci-clamp diode when enabled ? ??10ma notes to table 1?4 : (1) all vcca pins must be powered to 2.5 v (even when plls are not used ) and must be powered up and powered down at the same time. (2) you must connect v ccd_pll to v ccint through a decoupling cap acitor and ferrite bead. (3) power supplies must rise monotonically. (4) v ccio for all i/o banks must be powered up during device operation. configurations pins are powered up by v ccio of i/o banks 3, 8, and 9 where i/o banks 3 and 9 only support v ccio of 1.5, 1.8, 2.5, 3.0, and 3.3 v. for fast passive parallel (fpp) co nfiguration mode, the v ccio level of i/o bank 8 must be powered up to 1.5, 1.8, 2.5, 3.0, and 3.3 v. (5) you must set v cc_clkin to 2.5 v if you use clkin as a high-speed serial interface (hssi) refclk or as a diffclk input. (6) the clkin pins in i/o banks 3b and 8b can support single-ended i/o standard when the pins are used to clock left pl ls in non-transceiver applications. (7) the por time for standard por ranges between 50 and 200 ms. v ccint , v cca , and v ccio of i/o banks 3, 8, and 9 must reach the recommended operating range within 50 ms. (8) the por time for fast por ranges between 3 and 9 ms. v ccint , v cca , and v ccio of i/o banks 3, 8, and 9 must reach the recommended operating range within 3 ms. table 1?4. recommended operating conditions for cyclone iv gx devices (part 2 of 2) symbol parameter conditions min typ max unit table 1?5. esd for cyclone iv devices gpios and hssi i/os symbol parameter passing voltage unit v esdhbm esd voltage using the hbm (gpios) (1) 2000 v esd using the hbm (hssi i/os) (2) 1000 v v esdcdm esd using the cdm (gpios) 500 v esd using the cdm (hssi i/os) (2) 250 v notes to table 1?5 : (1) the passing voltage for ep4cgx 15 and ep4cgx30 row i/os is 1000v. (2) this value is applicable onl y to cyclone iv gx devices.
chapter 1: cyclone iv device datasheet 1?7 operating conditions december 2013 altera corporation cyclone iv device handbook, volume 3 dc characteristics this section lists the i/o leakage current, pin capacitance, on-chip termination (oct) tolerance, and bus hold specifications for cyclone iv devices. supply current the device supply current requirement is the minimum current drawn from the power supply pins that can be used as a reference for power size planning. use the excel-based early power estimator (epe) to get the supply current estimates for your design because these currents vary greatly with the resources used. table 1?6 lists the i/o pin leakage current for cyclone iv devices. bus hold the bus hold retains the last valid logic stat e after the source driving it either enters the high impedance state or is removed. ea ch i/o pin has an option to enable bus hold in user mode. bus hold is always disabled in configuration mode. table 1?7 lists bus hold specifications for cyclone iv devices. table 1?6. i/o pin leakage current for cyclone iv devices (1) , (2) symbol parameter conditions device min typ max unit i i input pin leakage current v i = 0 v to v cciomax ? ?10 ? 10 ? a i oz tristated i/o pin leakage current v o = 0 v to v cciomax ? ?10 ? 10 ? a notes to table 1?6 : (1) this value is specified for normal device operation. the value varies during device power - up. this applies for all v ccio settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 v). (2) the 10 ? a i/o leakage current limit is appl icable when the internal clamping diode is off. a higher current can be observed when the di ode is on. table 1?7. bus hold parameter for cyclone iv devices (part 1 of 2) (1) parameter condition v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max bus hold low, sustaining current v in > v il (maximum) 8 ? 12 ? 30?50?70?70? ? a bus hold high, sustaining current v in < v il (minimum) ?8 ? ?12 ? ?30 ? ?50 ? ?70 ? ?70 ? ? a bus hold low, overdrive current 0 v < v in < v ccio ? 125 ? 175 ? 200 ? 300 ? 500 ? 500 ? a bus hold high, overdrive current 0 v < v in < v ccio ? ?125 ? ?175 ? ?200 ? ?300 ? ?500 ? ?500 ? a
1?8 chapter 1: cyclone iv device datasheet operating conditions cyclone iv device handbook, december 2013 altera corporation volume 3 oct specifications table 1?8 lists the variation of oct without calibration across process, temperature, and voltage (pvt). oct calibration is automatically performe d at device power-up for oct-enabled i/os. table 1?9 lists the oct calibration a ccuracy at device power-up. bus hold trip point ? 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 v note to table 1?7 : (1) bus hold trip points are based on the calcu lated input voltages from the jedec standard. table 1?7. bus hold parameter for cyclone iv devices (part 2 of 2) (1) parameter condition v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max table 1?8. series oct without calibration specifications for cyclone iv devices description v ccio (v) resistance tolerance unit commercial maximum industrial, extended industrial, and automotive maximum series oct without calibration 3.0 30 40 % 2.5 30 40 % 1.8 40 50 % 1.5 50 50 % 1.2 50 50 % table 1?9. series oct with calibration at device power - up specifications for cyclone iv devices description v ccio (v) calibration accuracy unit commercial maximum industrial, extended industrial, and automotive maximum series oct with calibration at device power - up 3.0 10 10 % 2.5 10 10 % 1.8 10 10 % 1.5 10 10 % 1.2 10 10 %
chapter 1: cyclone iv device datasheet 1?9 operating conditions december 2013 altera corporation cyclone iv device handbook, volume 3 the oct resistance may vary with the va riation of temperature and voltage after calibration at device power-up. use table 1?10 and equation 1?1 to determine the final oct resistance considering the variations after calibration at device power-up. table 1?10 lists the change percentage of the oct resistance with voltage and temperature. table 1?10. oct variation after calibration at device power - up for cyclone iv devices nominal voltage dr/dt (%/c) dr/dv (%/mv) 3.0 0.262 ?0.026 2.5 0.234 ?0.039 1.8 0.219 ?0.086 1.5 0.199 ?0.136 1.2 0.161 ?0.288 equation 1?1. final oct resistance (1) , (2) , (3) , (4) , (5) , (6) ? r v = (v 2 ? v 1 ) 1000 dr/dv ????? (7) ? r t = (t 2 ? t 1 ) dr/dt ????? (8) for ? r x < 0; mf x = 1/ (| ? r x |/100 + 1) ????? (9) for ? r x > 0; mf x = ? r x /100 + 1 ????? (10) mf = mf v mf t ????? (11) r final = r initial mf ????? (12) notes to equation 1?1 : (1) t 2 is the final temperature. (2) t 1 is the initial temperature. (3) mf is multiplication factor. (4) r final is final resistance. (5) r initial is initial resistance. (6) subscript x refers to both v and t . (7) ? r v is a variation of resistance with voltage. (8) ? r t is a variation of resistance with temperature. (9) dr/dt is the change percentage of resistance with temperature after calibration at device power - up. (10) dr/dv is the change percentage of resistan ce with voltage after cal ibration at device power - up. (11) v 2 is final voltage. (12) v 1 is the initial voltage.
1?10 chapter 1: cyclone iv device datasheet operating conditions cyclone iv device handbook, december 2013 altera corporation volume 3 example 1?1 shows how to calculate the change of 50- ?? i/o impedance from 25c at 3.0 v to 85c at 3.15 v. pin capacitance table 1?11 lists the pin capacitance for cyclone iv devices. example 1?1. impedance change ? r v = (3.15 ? 3) 1000 ?0.026 = ?3.83 ? r t = (85 ? 25) 0.262 = 15.72 because ? r v is negative, mf v = 1 / (3.83/100 + 1) = 0.963 because ? r t is positive, mf t = 15.72/100 + 1 = 1.157 mf = 0.963 1.157 = 1.114 r final = 50 1.114 = 55.71 ? table 1?11. pin capacitance for cyclone iv devices (1) symbol parameter typical ? quad flat pack (qfp) typical ? quad flat no leads (qfn) typical ? ball-grid array (bga) unit c iotb input capacitance on top and bottom i/o pins 7 7 6 pf c iolr input capacitance on right i/o pins 7 7 5 pf c lvdslr input capacitance on right i/o pins with dedicated lvds output 8 8 7 pf c vreflr (2) input capacitance on right dual - purpose vref pin when used as v ref or user i/o pin 21 21 21 pf c vreftb (2) input capacitance on top and bottom dual - purpose vref pin when used as v ref or user i/o pin 23 (3) 23 23 pf c clktb input capacitance on top and bottom dedicated clock input pins 7 7 6 pf c clklr input capacitance on right dedicated clock input pins 6 6 5 pf notes to table 1?11 : (1) the pin capacitance applies to fbga, ubga, and mbga packages. (2) when you use the vref pin as a regular input or outp ut, you can expect a reduced perf ormance of toggle rate and t co because of higher pin capacitance. (3) c vreftb for the ep4ce22 device is 30 pf.
chapter 1: cyclone iv device datasheet 1?11 operating conditions december 2013 altera corporation cyclone iv device handbook, volume 3 internal weak pull-up and weak pull-down resistor table 1?12 lists the weak pull-up and pull-down resistor values for cyclone iv devices. hot-socketing table 1?13 lists the hot-socketing specifications for cyclone iv devices. 1 during hot-socketing, the i/o pin capacita nce is less than 15 pf and the clock pin capacitance is less than 20 pf. table 1?12. internal weak pull - up and weak pull - down resistor values for cyclone iv devices (1) symbol parameter conditions min typ max unit r _pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if you enable the programmable pull-up resistor option v ccio = 3.3 v 5% (2) , (3) 72541k ? v ccio = 3.0 v 5% (2) , (3) 72847k ? v ccio = 2.5 v 5% (2) , (3) 83561k ? v ccio = 1.8 v 5% (2) , (3) 10 57 108 k ? v ccio = 1.5 v 5% (2) , (3) 13 82 163 k ? v ccio = 1.2 v 5% (2) , (3) 19 143 351 k ? r _pd value of the i/o pin pull-down resistor before and during configuration v ccio = 3.3 v 5% (4) 61930k ? v ccio = 3.0 v 5% (4) 62236k ? v ccio = 2.5 v 5% (4) 62543k ? v ccio = 1.8 v 5% (4) 73571k ? v ccio = 1.5 v 5% (4) 8 50 112 k ? notes to table 1?12 : (1) all i/o pins have an option to enable weak pull - up except the configuration, test, and jtag pins. the weak pull - down feature is only available for jtag tck . (2) pin pull - up resistance values m ay be lower if an external source drives the pin higher than v ccio . (3) r _pu = (v ccio ?v i )/i r_pu minimum condition: ?40c; v ccio = v cc + 5%, v i = v cc + 5% ? 50 mv; typical condition: 25c; v ccio = v cc , v i = 0 v; maximum condition: 100c; v ccio = v cc ? 5%, v i = 0 v; in which v i refers to the input voltage at the i/o pin. (4) r _pd = v i /i r_pd minimum condition: ?40c; v ccio = v cc + 5%, v i = 50 mv; typical condition: 25c; v ccio = v cc , v i = v cc ?5%; maximum condition: 100c; v ccio = v cc ? 5%, v i = v cc ? 5%; in which v i refers to the input voltage at the i/o pin. table 1?13. hot - socketing specifications for cyclone iv devices symbol parameter maximum i iopin(dc) dc current per i/o pin 300 ? a i iopin(ac) ac current per i/o pin 8 ma (1) i xcvrtx(dc) dc current per transceiver tx pin 100 ma i xcvrrx(dc) dc current per transceiver rx pin 50 ma note to table 1?13 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |iiopin| = c dv/dt, in which c is the i/o pin capacitance and dv/dt is the slew rate.
1?12 chapter 1: cyclone iv device datasheet operating conditions cyclone iv device handbook, december 2013 altera corporation volume 3 schmitt trigger input cyclone iv devices support sc hmitt trigger input on the tdi , tms , tck , nstatus , nconfig , nce , conf_done , and dclk pins. a schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rate. table 1?14 lists the hysteresis specifications across the supported v ccio range for schmitt trigger inputs in cyclone iv devices. i/o standard specifications the following tables list input voltage sensitivities (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ), for various i/o standards supported by cyclone iv devices. table 1?15 through table 1?20 provide the i/o standard specifications for cyclone iv devices. table 1?14. hysteresis specifications for schmitt trigger input in cyclone iv devices symbol parameter conditions (v) minimum unit v schmitt hysteresis for schmitt trigger input v ccio = 3.3 200 mv v ccio = 2.5 200 mv v ccio = 1.8 140 mv v ccio = 1.5 110 mv table 1?15. single - ended i/o standard specifications for cyclone iv devices (1) , (2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) (4) i oh (ma) (4) min typ max min max min max max min 3.3 - v lvttl (3) 3.135 3.3 3.465 ? 0.8 1.7 3.6 0.45 2.4 4 ?4 3.3 - v lvcmos (3) 3.135 3.3 3.465 ? 0.8 1.7 3.6 0.2 v ccio ? 0.2 2 ?2 3.0 - v lvttl (3) 2.85 3.0 3.15 ?0.3 0.8 1.7 v ccio + 0.3 0.45 2.4 4 ?4 3.0 - v lvcmos (3) 2.85 3.0 3.15 ?0.3 0.8 1.7 v ccio + 0.3 0.2 v ccio ? 0.2 0.1 ?0.1 2.5 v (3) 2.375 2.5 2.625 ?0.3 0.7 1.7 v ccio + 0.3 0.4 2.0 1 ?1 1.8 v 1.71 1.8 1.89 ?0.3 0.35 x v ccio 0.65 x v ccio 2.25 0.45 v ccio ? 0.45 2?2 1.5 v 1.425 1.5 1.575 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2 1.2 v 1.14 1.2 1.26 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2 3.0-v pci 2.85 3.0 3.15 ? 0.3 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 3.0-v pci-x 2.85 3.0 3.15 ? 0.35 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 notes to table 1?15 : (1) for voltage - referenced receiver input waveform and explanation of terms used in table 1?15 , refer to ?glossary? on page 1?37 . (2) ac load cl = 10 pf (3) for more information about interfaci ng cyclone iv devices with 3.3/3.0/2.5 - v lvttl/lvcmos i/o standards, refer to an 447: interfacing cyclone iii and cyclone iv devices with 3.3/3.0/2.5-v lvttl/lvcmos i/o systems . (4) to meet the i ol and i oh specifications, you must set the current strength settings accordin gly. for example, to meet the 3.3-v lvttl specification (4 ma), set the current strength settings to 4 ma or higher . setting at lower current st rength may not meet the i ol and i oh specifications in the handbook.
chapter 1: cyclone iv device datasheet 1?13 operating conditions december 2013 altera corporation cyclone iv device handbook, volume 3 table 1?16. single - ended sstl and hstl i/o reference voltage specifications for cyclone iv devices (1) i/o standard v ccio (v) v ref (v) v tt (v) (2) min typ max min typ max min typ max sstl - 2 class i, ii 2.375 2.5 2.625 1.19 1.25 1.31 v ref ? 0.04 v ref v ref + 0.04 sstl - 18 class i, ii 1.7 1.8 1.9 0.833 0.9 0.969 v ref ? 0.04 v ref v ref + 0.04 hstl - 18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95 hstl - 15 class i, ii 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79 hstl - 12 class i, ii 1.14 1.2 1.26 0.48 x v ccio (3) 0.5 x v ccio (3) 0.52 x v ccio (3) ? 0.5 x v ccio ? 0.47 x v ccio (4) 0.5 x v ccio (4) 0.53 x v ccio (4) notes to table 1?16 : (1) for an explanation of terms used in table 1?16 , refer to ?glossary? on page 1?37 . (2) v tt of the transmitting device must track v ref of the receiving device. (3) value shown refers to dc input reference voltage, v ref(dc) . (4) value shown refers to ac input reference voltage, v ref(ac) . table 1?17. single - ended sstl and hstl i/o standards signal specifications for cyclone iv devices i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max min max min max max min sstl - 2 class i ? v ref ? 0.18 v ref + 0.18 ?? v ref ? 0.35 v ref + 0.35 ? v tt ? 0.57 v tt + 0.57 8.1 ?8.1 sstl - 2 class ii ? v ref ? 0.18 v ref + 0.18 ?? v ref ? 0.35 v ref + 0.35 ? v tt ? 0.76 v tt + 0.76 16.4 ?16.4 sstl - 18 class i ? v ref ? 0.125 v ref + 0.125 ?? v ref ? 0.25 v ref + 0.25 ? v tt ? 0.475 v tt + 0.475 6.7 ?6.7 sstl - 18 class ii ? v ref ? 0.125 v ref + 0.125 ?? v ref ? 0.25 v ref + 0.25 ?0.28 v ccio ? 0.28 13.4 ?13.4 hstl - 18 class i ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 8?8 hstl - 18 class ii ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 16 ?16 hstl - 15 class i ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 8?8 hstl - 15 class ii ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 16 ?16 hstl - 12 class i ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 ?0.24 v ref ? 0.15 v ref + 0.15 v ccio + 0.24 0.25 v ccio 0.75 v ccio 8?8 hstl - 12 class ii ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 ?0.24 v ref ? 0.15 v ref + 0.15 v ccio + 0.24 0.25 v ccio 0.75 v ccio 14 ?14
1?14 chapter 1: cyclone iv device datasheet operating conditions cyclone iv device handbook, december 2013 altera corporation volume 3 f for more information about receiver input and transmitter output waveforms, and for other differential i/o standards, refer to the i/o features in cyclone iv devices chapter . table 1?18. differential sstl i/o standard specifications for cyclone iv devices (1) i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl - 2 class i, ii 2.375 2.5 2.625 0.36 v ccio v ccio /2 ? 0.2 ? v ccio /2 + 0.2 0.7 v cci o v ccio /2 ? 0.125 ? v ccio /2 + 0.125 sstl - 18 class i, ii 1.7 1.8 1.90 0.25 v ccio v ccio /2 ? 0.175 ? v ccio /2 + 0.175 0.5 v cci o v ccio /2 ? 0.125 ? v ccio /2 + 0.125 note to table 1?18 : (1) differential sstl requires a v ref input. table 1?19. differential hstl i/o standard specifications for cyclone iv devices (1) i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max mi n max hstl - 18 class i, ii 1.71 1.8 1.89 0.2 ? 0.85 ? 0.95 0.85 ? 0.95 0.4 ? hstl - 15 class i, ii 1.425 1.5 1.575 0.2 ? 0.71 ? 0.79 0.71 ? 0.79 0.4 ? hstl - 12 class i, ii 1.14 1.2 1.26 0.16 v ccio 0.48 x v ccio ? 0.52 x v ccio 0.48 x v ccio ? 0.52 x v ccio 0.3 0.48 x v ccio note to table 1?19 : (1) differential hstl requires a v ref input. table 1?20. differential i/o standard specifications for cyclone iv devices (1) (part 1 of 2) i/o standard v ccio (v) v id (mv) v icm (v) (2) v od (mv) (3) v os (v) (3) min typ max min max min condition max min typ max min typ max lvpecl (row i/os) (6) 2.375 2.5 2.625 100 ? 0.05 d max ??? 500 mbps 1.80 ??? ? ? ? 0.55 500 mbps ? d max ? 700 mbps 1.80 1.05 d max > 700 mbps 1.55 lvpecl (column i/os) (6) 2.375 2.5 2.625 100 ? 0.05 d max ?? 500 mbps 1.80 ??? ? ? ? 0.55 500 mbps ? d max ?? 700 mbps 1.80 1.05 d max > 700 mbps 1.55 lvds (row i/os) 2.375 2.5 2.625 100 ? 0.05 d max ?? 500 mbps 1.80 247 ? 600 1.125 1.25 1.375 0.55 500 mbps ? d max ? 700 mbps 1.80 1.05 d max > 700 mbps 1.55
chapter 1: cyclone iv device datasheet 1?15 operating conditions december 2013 altera corporation cyclone iv device handbook, volume 3 lvds (column i/os) 2.375 2.5 2.625 100 ? 0.05 d max ? 500 mbps 1.80 247 ? 600 1.125 1.25 1.375 0.55 500 mbps ? d max ? 700 mbps 1.80 1.05 d max > 700 mbps 1.55 blvds (row i/os) (4) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? blvds (column i/os) (4) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? mini - lvds (row i/os) (5) 2.375 2.5 2.625 ? ? ? ? ? 300 ? 600 1.0 1.2 1.4 mini - lvds (column i/os) (5) 2.375 2.5 2.625 ? ? ? ? ? 300 ? 600 1.0 1.2 1.4 rsds ? (row i/os) (5) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.5 rsds (column i/os) (5) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.5 ppds (row i/os) (5) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.4 ppds (column i/os) (5) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.4 notes to table 1?20 : (1) for an explanation of terms used in table 1?20 , refer to ?glossary? on page 1?37 . (2) v in range: 0 v ? v in ? 1.85 v. (3) r l range: 90 ? r l ? 110 ? . (4) there are no fixed v in , v od , and v os specifications for blvds. they depend on the system topology. (5) the mini - lvds, rsds, and ppds standards are only supported at the output pins. (6) the lvpecl i/o standard is only suppor ted on dedicated clock input pins. this i/o standard is not supported for output pins. table 1?20. differential i/o standard specifications for cyclone iv devices (1) (part 2 of 2) i/o standard v ccio (v) v id (mv) v icm (v) (2) v od (mv) (3) v os (v) (3) min typ max min max min condition max min typ max min typ max
1?16 chapter 1: cyclone iv device datasheet power consumption cyclone iv device handbook, december 2013 altera corporation volume 3 power consumption use the following methods to estimate power for a design: the excel-based epe the quartus ? ii powerplay power analyzer feature the interactive excel-based epe is used prior to designing the device to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. the powerplay power analyzer can apply a combination of user-entered, simulation-derived, and es timated signal activities that, combined with detailed circuit models, can yield very accurate power estimates. f for more information about power estimation tools, refer to the early power estimator user guide and the powerplay power analysis chapter in volume 3 of the quartus ii handboo k. switching characteristics this section provides performance characte ristics of cyclone iv core and periphery blocks for commercial grade devices. these characteristics can be desi gnated as preliminary or final. preliminary characteristics are created usin g simulation results, process data, and other known parameters. the upper-right hand corner of these tables show the designation as ?preliminary?. final numbers are based on actual sili con characterization and testing. the numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. there are no designations on finalized tables.
chapter 1: cyclone iv device datasheet 1?17 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 transceiver performance specifications table 1?21 lists the cyclone iv gx transceiver specifications. table 1?21. transceiver specification for cyclone iv gx devices (part 1 of 4) symbol/ description conditions c6 c7, i7 c8 unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.5 v pcml, 3.3 v pcml, differential lvpecl, lvds, hcsl input frequency from refclk input pins ? 50 ? 156.25 50 ? 156.25 50 ? 156.25 mhz spread-spectrum modulating clock frequency physical interface for pci express (pipe) mode 30 ? 33 30 ? 33 30 ? 33 khz spread-spectrum downspread pipe mode ? 0 to ? 0.5% ?? 0 to ? 0.5% ?? 0 to ? 0.5% ?? peak-to-peak differential input voltage ? 0.1 ? 1.6 0.1 ? 1.6 0.1 ? 1.6 v v icm (ac coupled) ? 1100 5% 1100 5% 1100 5% mv v icm (dc coupled) hcsl i/o standard for pcie reference clock 250 ? 550 250 ? 550 250 ? 550 mv transmitter refclk phase noise (1) frequency offset = 1mhz ? 8mhz ?? ? 123 ? ? ? 123 ? ? ? 123 dbc/hz transmitter refclk total jitter (1) ? ? 42.3 ? ? 42.3 ? ? 42.3 ps r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ? ? transceiver clock cal_blk_clk clock frequency ? 10 ? 125 10 ? 125 10 ? 125 mhz fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz reconfig_clk clock frequency dynamic reconfiguration clock frequency 2.5/ 37.5 (2) ?50 2.5/ 37.5 (2) ?50 2.5/ 37.5 (2) ?50mhz delta time between reconfig_clk ???2??2??2ms transceiver block minimum power-down pulse width ??1??1??1?s
1?18 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 receiver supported i/o standards 1.4 v pcml, 1.5 v pcml, 2.5 v pcml, lvpecl, lvds data rate (f324 and smaller package) (15) ? 600 ? 2500 600 ? 2500 600 ? 2500 mbps data rate (f484 and larger package) (15) ? 600 ? 3125 600 ? 3125 600 ? 2500 mbps absolute v max for a receiver pin (3) ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v operational v max for a receiver pin ? ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a receiver pin ? ? 0.4 ? ? ? 0.4 ? ? ? 0.4 ? ? v peak-to-peak differential input voltage v id (diff p-p) v icm = 0.82 v setting, data rate = 600 mbps to 3.125 gbps 0.1 ? 2.7 0.1 ? 2.7 0.1 ? 2.7 v v icm v icm = 0.82 v setting ? 820 10% ?? 820 10% ?? 820 10% ?mv differential on-chip termination resistors 100 ?? setting ? 100 ? ? 100 ? ? 100 ? ? 150 ?? setting ? 150 ? ? 150 ? ? 150 ? ? differential and common mode return loss pipe, serial rapid i/o sr, sata, cpri lv, sdi, xaui compliant ? programmable ppm detector (4) ? 62.5, 100, 125, 200, 250, 300 ppm clock data recovery (cdr) ppm tolerance (without spread-spectrum clocking enabled) ??? 300 (5) , 350 (6) , (7) ?? 300 (5) , 350 (6) , (7) ?? 300 (5) , 350 (6) , (7) ppm cdr ppm tolerance (with synchronous spread-spectrum clocking enabled) (8) ??? 350 to ?5350 (7) , (9) ?? 350 to ?5350 (7) , (9) ?? 350 to ?5350 (7) , (9) ppm run length ? ? 80 ? ? 80 ? ? 80 ? ui programmable equalization no equalization ? ? 1.5 ? ? 1.5 ? ? 1.5 db medium low ? ? 4.5 ? ? 4.5 ? ? 4.5 db medium high ? ? 5.5 ? ? 5.5 ? ? 5.5 db high ? ? 7 ? ? 7 ? ? 7 db table 1?21. transceiver specification for cyclone iv gx devices (part 2 of 4) symbol/ description conditions c6 c7, i7 c8 unit min typ max min typ max min typ max
chapter 1: cyclone iv device datasheet 1?19 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 signal detect/loss threshold pipe mode 65 ? 175 65 ? 175 65 ? 175 mv t ltr (10) ? ?? 75 ?? 75?? 75 s t ltr-ltd_manual (11) ? 15? ? 15? ?15? ? s t ltd (12) ? 0 100 4000 0 100 4000 0 100 4000 ns t ltd_manual (13) ? ? ? 4000 ? ? 4000 ? ? 4000 ns t ltd_auto (14) ? ? ? 4000 ? ? 4000 ? ? 4000 ns receiver buffer and cdr offset cancellation time (per channel) ? ? ? 17000 ? ? 17000 ? ? 17000 recon fig_c lk cycles programmable dc gain dc gain setting = 0 ?0 ? ?0 ??0 ? db dc gain setting = 1 ?3 ? ?3 ??3 ? db dc gain setting = 2 ?6 ? ?6 ??6 ? db transmitter supported i/o standards 1.5 v pcml data rate (f324 and smaller package) ? 600 ? 2500 600 ? 2500 600 ? 2500 mbps data rate (f484 and larger package) ? 600 ? 3125 600 ? 3125 600 ? 2500 mbps v ocm 0.65 v setting ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 100 ?? setting ? 100 ? ? 100 ? ? 100 ? ? 150 ?? setting ? 150 ? ? 150 ? ? 150 ? ? differential and common mode return loss pipe, cpri lv, serial rapid i/o sr, sdi, xaui, sata compliant ? rise time ? 50 ? 200 50 ? 200 50 ? 200 ps fall time ? 50 ? 200 50 ? 200 50 ? 200 ps intra-differential pair skew ? ? ? 15 ? ? 15 ? ? 15 ps intra-transceiver block skew ? ? ? 120 ? ? 120 ? ? 120 ps table 1?21. transceiver specification for cyclone iv gx devices (part 3 of 4) symbol/ description conditions c6 c7, i7 c8 unit min typ max min typ max min typ max
1?20 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 pld-transceiver interface interface speed (f324 and smaller package) ? 25 ? 125 25 ? 125 25 ? 125 mhz interface speed (f484 and larger package) ? 25 ? 156.25 25 ? 156.25 25 ? 156.25 mhz digital reset pulse width ? minimum is 2 parallel clock cycles notes to table 1?21 : (1) this specification is valid for transmi tter output jitter specificati on with a maximum total jitte r value of 112 ps, typicall y for 3.125 gbps srio and xaui protocols. (2) the minimum reconfig_clk frequency is 2.5 mhz if the tran sceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5 mhz if the transceiver channel is configured in receiver only or receiver and transmitter mode. (3) the device cannot tolerate prolonged operation at this absolute maximum. (4) the rate matcher supports only up to 300 parts per million (ppm). (5) supported for the n148, f169 , and f324 device packages only. (6) supported for the f484, f672, and f896 devi ce packages only. pending device characterization. (7) to support cdr ppm tolerance greater than 300 ppm, implement ppm detector in user logic and configure cdr to manual lock mo de. (8) asynchronous spread-spectrum clocking is not supported. (9) for the ep4cgx30 (f484 package only ), ep4cgx50, and ep4cgx75 devices, the cdr ppl tolerance is 200 ppm. (10) time taken until pll_locked goes high after pll_powerdown deasserts. (11) time that the cdr must be kep t in lock-to-reference mode after rx_analogreset deasserts and before rx_locktodata is asserted in manual mode. (12) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode ( figure 1?2 ), or after rx_freqlocked signal goes high in automatic mode ( figure 1?3 ). (13) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. (14) time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. (15) to support data rates lower than the minimum specification through oversampling, use the cdr in ltr mode only. table 1?21. transceiver specification for cyclone iv gx devices (part 4 of 4) symbol/ description conditions c6 c7, i7 c8 unit min typ max min typ max min typ max
chapter 1: cyclone iv device datasheet 1?21 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 figure 1?2 shows the lock time parameters in manual mode. 1 ltd = lock-to-data. ltr = lock-to-reference. figure 1?3 shows the lock time para meters in automatic mode. figure 1?2. lock time parameters for manual mode rx _ analogreset rx _ digitalreset reset signals output status signals rx _ locktorefclk 2 3 4 cdr control signals rx _ locktodata 3 busy 1 two parallel clock cycles ltd_manual (2) t ltr_ltd_manual (1) t figure 1?3. lock time parameters for automatic mode reset signals rx _ analogreset 2 output status signals rx _ freqlocked 3 rx _ digitalreset 4 busy 1 two parallel clock cycles ltd_auto (1) t
1?22 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 figure 1?4 shows the differential receiver input waveform. figure 1?5 shows the transmitter output waveform. table 1?22 lists the typical v od for tx term that equals 100 ? . figure 1?4. receiver input waveform single-ended waveform differential waveform v id (diff peak-peak) = 2 x v id (single-ended) positive channel (p) negative channel (n) gro u nd v id v id v id p ? n = 0 v v cm figure 1?5. transmitter output waveform single-ended waveform differential waveform v od (diff peak-peak) = 2 x v od (single-ended) positive channel (p) negative channel (n) gro u nd v od v od v od p ? n = 0 v v cm table 1?22. typical v od setting, tx term = 100 ? symbol v od setting (mv) 1234 (1) 56 v od differential peak to peak typical (mv) 400 600 800 900 1000 1200 note to table 1?22 : (1) this setting is required for compliance with the pcie protocol.
chapter 1: cyclone iv device datasheet 1?23 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 table 1?23 lists the cyclone iv gx transceiver block ac specifications. core performance specifications the following sections describe the clock tree specifications, plls, embedded multiplier, memory block, and configuration specifications for cyclone iv devices. clock tree specifications table 1?24 lists the clock tree specifications for cyclone iv devices. table 1?23. transceiver block ac specification for cyclone iv gx devices (1) , (2) symbol/ description conditions c6 c7, i7 c8 unit min typ max min typ max min typ max pcie transmit jitter generation (3) total jitter at 2.5 gbps (gen1) compliance pattern ? ? 0.25 ? ? 0.25 ? ? 0.25 ui pcie receiver jitter tolerance (3) total jitter at 2.5 gbps (gen1) compliance pattern > 0.6 > 0.6 > 0.6 ui gige transmit jitter generation (4) deterministic jitter (peak-to-peak) pattern = crpat ??0.14??0.14??0.14ui total jitter (peak-to-peak) pattern = crpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui gige receiver jitter tolerance (4) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 > 0.66 > 0.66 ui notes to table 1?23 : (1) dedicated refclk pins were used to dri ve the input reference clocks. (2) the jitter numbers specified are va lid for the stated conditions only. (3) the jitter numbers for pipe are comp liant to the pcie base specification 2.0. (4) the jitter numbers for gige are compli ant to the ieee802.3-2002 specification. table 1?24. clock tree performance for cyclone iv devices (part 1 of 2) device performance unit c6 c7 c8 c8l (1) c9l (1) i7 i8l (1) a7 ep4ce6 500 437.5 402 362 265 437.5 362 402 mhz EP4CE10 500 437.5 402 362 265 437.5 362 402 mhz ep4ce15 500 437.5 402 362 265 437.5 362 402 mhz ep4ce22 500 437.5 402 362 265 437.5 362 402 mhz ep4ce30 500 437.5 402 362 265 437.5 362 402 mhz ep4ce40 500 437.5 402 362 265 437.5 362 402 mhz
1?24 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 pll specifications table 1?25 lists the pll specifications for cyclone iv devices when operating in the commercial junction temperature range (0c to 85c), the industrial junction temperature range (?40c to 100c), the ex tended industrial junction temperature range (?40c to 125c), and the automotive junction temperature range (?40c to 125c). for more information about the pll block, refer to ?glossary? on page 1?37 . ep4ce55 500 437.5 402 362 265 437.5 362 ? mhz ep4ce75 500 437.5 402 362 265 437.5 362 ? mhz ep4ce115 ? 437.5 402 362 265 437.5 362 ? mhz ep4cgx15 500 437.5 402 ? ? 437.5 ? ? mhz ep4cgx22 500 437.5 402 ? ? 437.5 ? ? mhz ep4cgx30 500 437.5 402 ? ? 437.5 ? ? mhz ep4cgx50 500 437.5 402 ? ? 437.5 ? ? mhz ep4cgx75 500 437.5 402 ? ? 437.5 ? ? mhz ep4cgx110 500 437.5 402 ? ? 437.5 ? ? mhz ep4cgx150 500 437.5 402 ? ? 437.5 ? ? mhz note to table 1?24 : (1) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. table 1?24. clock tree performance for cyclone iv devices (part 2 of 2) device performance unit c6 c7 c8 c8l (1) c9l (1) i7 i8l (1) a7 table 1?25. pll specifications for cyclone iv devices (1), (2) (part 1 of 2) symbol parameter min typ max unit f in (3) input clock frequency (?6, ?7, ?8 speed grades) 5 ? 472.5 mhz input clock frequency (?8l speed grade) 5 ? 362 mhz input clock frequency (?9l speed grade) 5 ? 265 mhz f inpfd pfd input frequency 5 ? 325 mhz f vco (4) pll internal vco operating range 600 ? 1300 mhz f induty input clock duty cycle 40 ? 60 % t injitter_ccj (5) input clock cycle-to-cycle jitter f ref ? 100 mhz ? ? 0.15 ui f ref < 100 mhz ? ? 750 ps f out_ext (external clock output) (3) pll output frequency ? ? 472.5 mhz f out (to global clock) pll output frequency (?6 speed grade) ? ? 472.5 mhz pll output frequency (?7 speed grade) ? ? 450 mhz pll output frequency (?8 speed grade) ? ? 402.5 mhz pll output frequency (?8l speed grade) ? ? 362 mhz pll output frequency (?9l speed grade) ? ? 265 mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t lock time required to lock from end of device configuration ? ? 1 ms
chapter 1: cyclone iv device datasheet 1?25 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 t dlock time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or areset is deasserted) ?? 1 ms t outjitter_period_dedclk (6) dedicated clock output period jitter f out ? 100 mhz ? ? 300 ps f out < 100 mhz ? ? 30 mui t outjitter_ccj_dedclk (6) dedicated clock output cycle-to-cycle jitter f out ? 100 mhz ? ? 300 ps f out < 100 mhz ? ? 30 mui t outjitter_period_io (6) regular i/o period jitter f out ? 100 mhz ? ? 650 ps f out < 100 mhz ? ? 75 mui t outjitter_ccj_io (6) regular i/o cycle-to-cycle jitter f out ? 100 mhz ? ? 650 ps f out < 100 mhz ? ? 75 mui t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on areset signal. 10 ? ? ns t configpll time required to reconfigure scan chains for plls ? 3.5 (7) ? scanclk cycles f scanclk scanclk frequency ? ? 100 mhz t casc_outjitter_period_dedclk (8) , (9) period jitter for dedicated clock output in cascaded plls (f out ? 100 mhz) ? ? 425 ps period jitter for dedicated clock output in cascaded plls (f out ? 100 mhz) ? ? 42.5 mui notes to table 1?25 : (1) this table is applicable for genera l purpose plls and multipurpose plls. (2) you must connect v ccd_pll to v ccint through the decoupling capacitor and fe rrite bead. (3) this parameter is limited in the quartu s ii software by the i/o maximum frequency. the maximum i/o frequency is different for each i/o standard. (4) the v co frequency reported by the quartus ii softw are in the pll summary section of the comp ilation report takes into consideration the v co post-scale counter k value. therefore, if the counter k has a va lue of 2, the frequency report ed can be lower than the f vco specification. (5) a high input jitter directly affects th e pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source that is less than 200 ps. (6) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the pll when an input jitter of 30 ps is applied. (7) with 100-mhz scanclk frequency. (8) the cascaded plls specification is appli cable only with the following conditions: upstream pll?0.59 mhz ? upstream pll bandwidth < 1 mhz downstream pll?downstr eam pll bandwidth > 2 mhz (9) pll cascading is not supported for transceiver applications. table 1?25. pll specifications for cyclone iv devices (1), (2) (part 2 of 2) symbol parameter min typ max unit
1?26 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 embedded multiplier specifications table 1?26 lists the embedded multiplier specifications for cyclone iv devices. memory block specifications table 1?27 lists the m9k memory block specifications for cyclone iv devices. configuration and jtag specifications table 1?28 lists the configuration mode specifications for cyclone iv devices. table 1?26. embedded multiplier specifications for cyclone iv devices mode resources used performance unit number of multipliers c6 c7, i7, a7 c8 c8l, i8l c9l 9 9-bit multiplier 1 340 300 260 240 175 mhz 18 18-bit multiplier 1 287 250 200 185 135 mhz table 1?27. memory block performance specifications for cyclone iv devices memory mode resources used performance unit les m9k memory c6 c7, i7, a7 c8 c8l, i8l c9l m9k block fifo 256 36 47 1 315 274 238 200 157 mhz single-port 256 36 0 1 315 274 238 200 157 mhz simple dual-port 256 36 clk 0 1 315 274 238 200 157 mhz true dual port 512 18 single clk 0 1 315 274 238 200 157 mhz table 1?28. passive configuration mode specifications for cyclone iv devices (1) programming mode v ccint voltage level (v) dclk f max unit passive serial (ps) 1.0 (3) 66 mhz 1.2 133 mhz fast passive parallel (fpp) (2) 1.0 (3) 66 mhz 1.2 (4) 100 mhz notes to table 1?28 : (1) for more information about ps and fpp conf iguration timing parameters, refer to the configuration and remote system upgrades in cyclone iv devices chapter. (2) fpp configuration mode supports all cyclone iv e devic es (except for e144 package devices) and ep4cgx50, ep4cgx75, ep4cgx110, and ep4cgx150 only. (3) v ccint = 1.0 v is only supported for cycl one iv e 1.0 v core voltage devices. (4) cyclone iv e devices support 1.2 v v ccint . cyclone iv e 1.2 v core voltage devices support 133 mhz dclk f max for ep4ce6, EP4CE10, ep4ce15, ep4ce2 2, ep4ce30, and ep4ce40 only.
chapter 1: cyclone iv device datasheet 1?27 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 table 1?29 lists the active configuration mode specifications for cyclone iv devices. table 1?30 lists the jtag timing parameters and values for cyclone iv devices. periphery performance this section describes periphery performanc e, including high-speed i/o and external memory interface. i/o performance supports several system interfaces, such as the high-speed i/o interface, external memory interface, and the pci/pci-x bus interface. i/os using the sstl-18 class i termination standard ca n achieve up to the stated ddr2 sdram interfacing speeds. i/os using general-purpose i/o standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-lvttl/lvcmos are capable of a typical 200 mhz interfacing frequency with a 10 pf load. table 1?29. active configuration mode specifications for cyclone iv devices programming mode dclk range typical dclk unit active parallel (ap) (1) 20 to 40 33 mhz active serial (as) 20 to 40 33 mhz note to table 1?29 : (1) ap configuration mode is only supported for cyclone iv e devices. table 1?30. jtag timing parameters for cyclone iv devices (1) symbol parameter min max unit t jcp tck clock period 40 ? ns t jch tck clock high time 19 ? ns t jcl tck clock low time 19 ? ns t jpsu_tdi jtag port setup time for tdi 1 ? ns t jpsu_tms jtag port setup time for tms 3 ? ns t jph jtag port hold time 10 ? ns t jpco jtag port clock to output (2) , (3) ?15ns t jpzx jtag port high impedance to valid output (2) , (3) ?15ns t jpxz jtag port valid output to high impedance (2) , (3) ?15ns t jssu capture register setup time 5 ? ns t jsh capture register hold time 10 ? ns t jsco update register clock to output ? 25 ns t jszx update register high impedance to valid output ? 25 ns t jsxz update register valid output to high impedance ? 25 ns notes to table 1?30 : (1) for more information abou t jtag waveforms, refer to ?jtag waveform? in ?glossary? on page 1?37 . (2) the specification is shown for 3.3-, 3.0-, and 2.5-v lvttl/lvcmos operation of jtag pins. for 1.8-v lvttl/lvcmos and 1.5-v lvcmos, the output time specification is 16 ns. (3) for ep4cgx22, ep4cgx30 (f324 an d smaller package), ep4cgx110, and ep 4cgx150 devices, the output time specification for 3.3-, 3.0-, and 2.5-v lvttl/lvcmos operation of jtag pins is 16 ns. for 1.8-v lvttl/lvcmos and 1.5-v lvcmos, the output time specification is 18 ns.
1?28 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 f for more information about the supported maximum clock rate, device and pin planning, ip implementation, and device termination, refer to section iii: system performance specifications of the external memory interfaces handbook . 1 actual achievable frequency depends on de sign- and system-specific factors. perform hspice/ibis simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. high-speed i/o specifications table 1?31 through table 1?36 list the high-speed i/o ti ming for cyclone iv devices. for definitions of high-speed timing specifications, refer to ?glossary? on page 1?37 . table 1?31. rsds transmitter timing specifications for cyclone iv devices (1) , (2) , (4) (part 1 of 2) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min typ max min typ max min typ max min typ max min typ max f hsclk (input clock frequency) 10 5 ? 180 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 8 5 ? 180 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 7 5 ? 180 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 4 5 ? 180 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 2 5 ? 180 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 1 5 ? 360 5 ? 311 5 ? 311 5 ? 311 5 ? 265 mhz device operation in mbps 10 100 ? 360 100 ? 311 100 ? 311 100 ? 311 100 ? 265 mbps 8 80 ? 360 80 ? 311 80 ? 311 80 ? 311 80 ? 265 mbps 7 70 ? 360 70 ? 311 70 ? 311 70 ? 311 70 ? 265 mbps 4 40 ? 360 40 ? 311 40 ? 311 40 ? 311 40 ? 265 mbps 2 20 ? 360 20 ? 311 20 ? 311 20 ? 311 20 ? 265 mbps 1 10 ? 360 10 ? 311 10 ? 311 10 ? 311 10 ? 265 mbps t duty ? 45 ? 55 45 ? 55 45 ? 55 45 ? 55 45 ? 55 % transmitter channel-to- channel skew (tccs) ? ? ? 200 ? ? 200 ? ? 200 ? ? 200 ? ? 200 ps output jitter (peak to peak) ? ? ? 500 ? ? 500 ? ? 550 ? ? 600 ? ? 700 ps t rise 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ? 500 ? ? 500 ? ps t fall 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ? 500 ? ? 500 ? ps
chapter 1: cyclone iv device datasheet 1?29 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 t lock (3) ? ??1??1?? 1??1??1ms notes to table 1?31 : (1) applicable for true rsds and emulated rsds_e_3r transmitter. (2) cyclone iv e devices?true rsds transmitter is only supported at the output pin of row i/o banks 1, 2, 5, and 6. emulated rsds transmitter is supported at the output pin of all i/o banks. cyclone iv gx devices?true rsds transmitter is only supported at the output pin of row i/o banks 5 and 6. emul ated rsds transmitt er is supported at the output pin of i/o banks 3, 4, 5, 6, 7, 8, and 9. (3) t lock is the time required fo r the pll to lock from the end-of-device configuration. (4) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. c yclone iv e 1.2 v core voltage devices only support c6, c7, c8, i7, and a7 speed grades. cyclone iv gx devices only su pport c6, c7, c8, and i7 speed grades. table 1?31. rsds transmitter timing specifications for cyclone iv devices (1) , (2) , (4) (part 2 of 2) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min typ max min typ max min typ max min typ max min typ max table 1?32. emulated rsds_e_1r transmitter timing specifications for cyclone iv devices (1), (3) (part 1 of 2) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min typ max min typ max min typ max min typ max min typ max f hsclk (input clock frequency) 10 5 ? 85 5 ? 85 5 ? 85 5 ? 85 5 ? 72.5 mhz 8 5 ? 85 5 ? 85 5 ? 85 5 ? 85 5 ? 72.5 mhz 7 5 ? 85 5 ? 85 5 ? 85 5 ? 85 5 ? 72.5 mhz 4 5 ? 85 5 ? 85 5 ? 85 5 ? 85 5 ? 72.5 mhz 2 5 ? 85 5 ? 85 5 ? 85 5 ? 85 5 ? 72.5 mhz 1 5 ? 170 5 ? 170 5 ? 170 5 ? 170 5 ? 145 mhz device operation in mbps 10 100 ? 170 100 ? 170 100 ? 170 100 ? 170 100 ? 145 mbps 8 80 ? 170 80 ? 170 80 ? 170 80 ? 170 80 ? 145 mbps 7 70 ? 170 70 ? 170 70 ? 170 70 ? 170 70 ? 145 mbps 4 40 ? 170 40 ? 170 40 ? 170 40 ? 170 40 ? 145 mbps 2 20 ? 170 20 ? 170 20 ? 170 20 ? 170 20 ? 145 mbps 1 10 ? 170 10 ? 170 10 ? 170 10 ? 170 10 ? 145 mbps t duty ? 45 ? 55 45 ? 55 45 ? 55 45 ? 55 45 ? 55 % tccs ? ? ? 200 ? ? 200 ? ? 200 ? ? 200 ? ? 200 ps output jitter (peak to peak) ? ? ? 500 ? ? 500 ? ? 550 ? ? 600 ? ? 700 ps t rise 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ? 500 ? ? 500 ? ps t fall 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ? 500 ? ? 500 ? ps
1?30 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 t lock (2) ? ??1??1??1??1?? 1 ms notes to table 1?32 : (1) emulated rsds_e_1r transmitter is supported at the output pin of all i/o banks of cyclone iv e devices and i/o banks 3, 4, 5, 6, 7, 8, and 9 of cyclone iv gx devices. (2) t lock is the time required fo r the pll to lock from the end-of-device configuration. (3) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, a nd i8l speed grades. cyclone iv e 1. 2 v core voltag e devices only support c6, c7, c8, i7, and a7 speed grades. cyclone iv g x devices only support c6, c7 , c8, and i7 speed grades. table 1?32. emulated rsds_e_1r transmitter timing specifications for cyclone iv devices (1), (3) (part 2 of 2) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min typ max min typ max min typ max min typ max min typ max table 1?33. mini-lvds transmitter timing specifications for cyclone iv devices (1) , (2) , (4) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min typ max min typ max min typ max min typ max min typ max f hsclk (input clock frequency) 10 5 ? 200 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 8 5 ? 200 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 7 5 ? 200 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 4 5 ? 200 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 2 5 ? 200 5 ? 155.5 5 ? 155.5 5 ? 155.5 5 ? 132.5 mhz 1 5 ? 400 5 ? 311 5 ? 311 5 ? 311 5 ? 265 mhz device operation in mbps 10 100 ? 400 100 ? 311 100 ? 311 100 ? 311 100 ? 265 mbps 8 80 ? 400 80 ? 311 80 ? 311 80 ? 311 80 ? 265 mbps 7 70 ? 400 70 ? 311 70 ? 311 70 ? 311 70 ? 265 mbps 4 40 ? 400 40 ? 311 40 ? 311 40 ? 311 40 ? 265 mbps 2 20 ? 400 20 ? 311 20 ? 311 20 ? 311 20 ? 265 mbps 1 10 ? 400 10 ? 311 10 ? 311 10 ? 311 10 ? 265 mbps t duty ? 45 ? 55 45 ? 55 45 ? 55 45 ? 55 45 ? 55 % tccs ? ? ? 200 ? ? 200 ? ? 200 ? ? 200 ? ? 200 ps output jitter (peak to peak) ? ? ? 500 ? ? 500 ? ? 550 ? ? 600 ? ? 700 ps t rise 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ? 500 ? ? 500 ? ps t fall 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ? 500 ? ? 500 ? ps t lock (3) ? ??1?? 1 ?? 1 ?? 1 ?? 1 ms notes to table 1?33 : (1) applicable for true and em ulated mini-lvds transmitter. (2) cyclone iv e?true mini-lvds transmitter is only supported at th e output pin of row i/o banks 1, 2, 5, and 6. emulated mini-lvd s transmitter is supported at the output pin of all i/o banks. cyclone iv gx?true mini-lvds transmitter is only supported at the output pin of row i/o banks 5 and 6. emulated mini-lvds transmi tter is supported at the output pin of i/o banks 3, 4, 5, 6, 7, 8, and 9. (3) t lock is the time required fo r the pll to lock from the end-of-device configuration. (4) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. cyclone iv e 1.2 v core voltage devices only support c6, c7, c8, i7, and a7 speed grades. cyclone iv g x devices only support c6, c7 , c8, and i7 speed grades.
chapter 1: cyclone iv device datasheet 1?31 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 table 1?34. true lvds transmitter timing specifications for cyclone iv devices (1) , (3) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min max min max min max min max min max f hsclk (input clock frequency) 10 5 420 5 370 5 320 5 320 5 250 mhz 8 5 420 5 370 5 320 5 320 5 250 mhz 7 5 420 5 370 5 320 5 320 5 250 mhz 4 5 420 5 370 5 320 5 320 5 250 mhz 2 5 420 5 370 5 320 5 320 5 250 mhz 1 5 420 5 402.5 5 402.5 5 362 5 265 mhz hsiodr 10 100 840 100 740 100 640 100 640 100 500 mbps 8 80 840 80 740 80 640 80 640 80 500 mbps 7 70 840 70 740 70 640 70 640 70 500 mbps 4 40 840 40 740 40 640 40 640 40 500 mbps 2 20 840 20 740 20 640 20 640 20 500 mbps 1 10 420 10 402.5 10 402.5 10 362 10 265 mbps t duty ?45554555455545554555% tccs ? ? 200 ? 200 ? 200 ? 200 ? 200 ps output jitter (peak to peak) ? ? 500 ? 500 ? 550 ? 600 ? 700 ps t lock (2) ??1?1?1?1?1ms notes to table 1?34 : (1) cyclone iv e?true lvds transmitter is only supported at the output pin of row i/o banks 1, 2, 5, and 6. cyclone iv gx?true lvds transmitter is only suppo rted at the output pin of row i/o banks 5 and 6. (2) t lock is the time required fo r the pll to lock from the end-of-device configuration. (3) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. cyclone iv e 1.2 v core voltage devices only support c6, c7, c8, i7, and a7 speed grades. cyclone iv gx d evices only support c6, c7, c8, and i7 speed grades. table 1?35. emulated lvds transmitter timing specifications for cyclone iv devices (1) , (3) (part 1 of 2) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min max min max min max min max min max f hsclk (input clock frequency) 10 5 320 5 320 5 275 5 275 5 250 mhz 8 5 320 5 320 5 275 5 275 5 250 mhz 7 5 320 5 320 5 275 5 275 5 250 mhz 4 5 320 5 320 5 275 5 275 5 250 mhz 2 5 320 5 320 5 275 5 275 5 250 mhz 1 5 402.5 5 402.5 5 402.5 5 362 5 265 mhz hsiodr 10 100 640 100 640 100 550 100 550 100 500 mbps 8 80 640 80 640 80 550 80 550 80 500 mbps 7 70 640 70 640 70 550 70 550 70 500 mbps 4 40 640 40 640 40 550 40 550 40 500 mbps 2 20 640 20 640 20 550 20 550 20 500 mbps 1 10 402.5 10 402.5 10 402.5 10 362 10 265 mbps
1?32 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 external memory interface specifications the external memory interfaces for cyclon e iv devices are auto-calibrating and easy to implement. t duty ? 455545554555455545 55% tccs ? ? 200 ? 200 ? 200 ? 200 ? 200 ps output jitter (peak to peak) ? ? 500 ? 500 ? 550 ? 600 ? 700 ps t lock (2) ??1?1?1?1? 1ms notes to table 1?35 : (1) cyclone iv e?emulated lvds transmitter is s upported at the output pin of all i/o banks. cyclone iv gx?emulated lvds transmitter is supported at the output pin of i/o banks 3, 4, 5, 6, 7, 8, and 9. (2) t lock is the time required fo r the pll to lock from the end-of-device configuration. (3) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. cyclone iv e 1.2 v core voltage devices only support c6, c7, c8, i7, and a7 speed grades. cyclone iv gx d evices only support c6, c7, c8, and i7 speed grades. table 1?35. emulated lvds transmitter timing specifications for cyclone iv devices (1) , (3) (part 2 of 2) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min max min max min max min max min max table 1?36. lvds receiver timing specifications for cyclone iv devices (1) , (3) symbol modes c6 c7, i7 c8, a7 c8l, i8l c9l unit min max min max min max min max min max f hsclk (input clock frequency) 10 10 437.5 10 370 10 320 10 320 10 250 mhz 8 10 437.5 10 370 10 320 10 320 10 250 mhz 7 10 437.5 10 370 10 320 10 320 10 250 mhz 4 10 437.5 10 370 10 320 10 320 10 250 mhz 2 10 437.5 10 370 10 320 10 320 10 250 mhz 1 10 437.5 10 402.5 10 402.5 10 362 10 265 mhz hsiodr 10 100 875 100 740 100 640 100 640 100 500 mbps 8 80 875 80 740 80 640 80 640 80 500 mbps 7 70 875 70 740 70 640 70 640 70 500 mbps 4 40 875 40 740 40 640 40 640 40 500 mbps 2 20 875 20 740 20 640 20 640 20 500 mbps 1 10 437.5 10 402.5 10 402.5 10 362 10 265 mbps sw ? ? 400 ? 400 ? 400 ? 550 ? 640 ps input jitter tolerance ? ? 500 ? 500 ? 550 ? 600 ? 700 ps t lock (2) ??1?1?1?1?1ms notes to table 1?36 : (1) cyclone iv e?lvds receiver is supported at all i/o banks. cyclone iv gx?lvds receiver is supported at i/o banks 3, 4, 5, 6, 7, 8, and 9. (2) t lock is the time required fo r the pll to lock from the end-of-device configuration. (3) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. cyclone iv e 1.2 v core voltage devices only support c6, c7, c8, i7, and a7 speed grades. cyclone iv gx d evices only support c6, c7, c8, and i7 speed grades.
chapter 1: cyclone iv device datasheet 1?33 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 f for more information about the supported maximum clock rate, device and pin planning, ip implementation, and device termination, refer to section iii: system performance specifications of the external memory interface handbook . table 1?37 lists the memory output clock jitter specifications for cyclone iv devices. duty cycle distortion specifications table 1?38 lists the worst case duty cycle distortion for cyclone iv devices. oct calibration timing specification table 1?39 lists the duration of calibration for series oct with calibration at device power-up for cyclone iv devices. table 1?37. memory output clock jitter specifications for cyclone iv devices (1) , (2) parameter symbol min max unit clock period jitter t jit(per) ?125 125 ps cycle-to-cycle period jitter t jit(cc) ?200 200 ps duty cycle jitter t jit(duty) ?150 150 ps notes to table 1?37 : (1) memory output cl ock jitter measurements are for 200 consecutive clock cycles, as specified in th e jedec ddr2 standard. (2) the clock jitter specification applies to memory output cl ock pins generated using ddio circuits clocked by a pll output routed on a global clock (gclk) network. table 1?38. duty cycle distortion on cyclone iv devices i/o pins (1) , (2), (3) symbol c6 c7, i7 c8, i8l, a7 c9l unit min max min max min max min max output duty cycle 4555455545554555 % notes to table 1?38 : (1) the duty cycle distortion specification appl ies to clock outputs from the plls, glob al clock tree, and ioe driving the dedic ated and general purpose i/o pins. (2) cyclone iv devices meet the specified duty cycle distortion at the maxi mum output toggle rate for each combination of i/o sta ndard and current strength. (3) cyclone iv e 1.0 v core voltage devices only support c8l, c9l, and i8l speed grades. cyclone iv e 1.2 v core voltage devices only support c6, c7, c8, i7, and a7 speed grades. cyclone iv gx d evices only support c6, c7, c8, and i7 speed grades. table 1?39. timing specification for series oct with calibration at device power-up for cyclone iv devices (1) symbol description maximum units t octcal duration of series oct with calibration at device power-up 20 s note to table 1?39 : (1) oct calibration takes place a fter device configuration and before entering user mode.
1?34 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 ioe programmable delay table 1?40 and table 1?41 list the ioe programmable delay for cyclone iv e 1.0 v core voltage devices. table 1?40. ioe programmable delay on column pins for cyclone iv e 1.0 v core voltage devices (1) , (2) parameter paths affected number of setting min offset max offset unit fast corner slow corner c8l i8l c8l c9l i8l input delay from pin to internal cells pad to i/o dataout to core 7 0 2.054 1.924 3.387 4.017 3.411 ns input delay from pin to input register pad to i/o input register 8 0 2.010 1.875 3.341 4.252 3.367 ns delay from output register to output pin i/o output register to pad 2 0 0.641 0.631 1.111 1.377 1.124 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.971 0.931 1.684 2.298 1.684 ns notes to table 1?40 : (1) the incremental values for th e settings are generally linear. for the exact va lues for each setting, use the latest version of the quartus ii software. (2) the minimum and maximum offset timing numbers are in reference to setting 0 as available in the quartus ii software. table 1?41. ioe programmable delay on row pins for cyclone iv e 1.0 v core voltage devices (1) , (2) parameter paths affected number of setting min offset max offset unit fast corner slow corner c8l i8l c8l c9l i8l input delay from pin to internal cells pad to i/o dataout to core 7 0 2.057 1.921 3.389 4.146 3.412 ns input delay from pin to input register pad to i/o input register 8 0 2.059 1.919 3.420 4.374 3.441 ns delay from output register to output pin i/o output register to pad 2 0 0.670 0.623 1.160 1.420 1.168 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.960 0.919 1.656 2.258 1.656 ns notes to table 1?41 : (1) the incremental values for th e settings are generally linear. for the exact va lues for each setting, use the latest version of the quartus ii software. (2) the minimum and maximum offset timing numbers are in reference to setting 0 as available in the quartus ii software.
chapter 1: cyclone iv device datasheet 1?35 switching characteristics december 2013 altera corporation cyclone iv device handbook, volume 3 table 1?42 and table 1?43 list the ioe programmable delay for cyclone iv e 1.2 v core voltage devices. table 1?42. ioe programmable delay on column pins for cyclone iv e 1.2 v core voltage devices (1) , (2) parameter paths affected number of setting min offset max offset unit fast corner slow corner c6 i7 a7 c6 c7 c8 i7 a7 input delay from pin to internal cells pad to i/o dataout to core 7 0 1.314 1.211 1.211 2.177 2.340 2.433 2.388 2.508 ns input delay from pin to input register pad to i/o input register 8 0 1.307 1.203 1.203 2.19 2.387 2.540 2.430 2.545 ns delay from output register to output pin i/o output register to pad 2 0 0.437 0.402 0.402 0.747 0.820 0.880 0.834 0.873 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.693 0.665 0.665 1.200 1.379 1.532 1.393 1.441 ns notes to table 1?42 : (1) the incremental values for the settings are generally linear. for the exact values fo r each setting, use the latest version of the quartus ii software. (2) the minimum and maximum offset timing numbers are in reference to setting 0 as available in the quartus ii software. table 1?43. ioe programmable delay on row pins for cyclone iv e 1.2 v core voltage devices (1) , (2) parameter paths affected number of setting min offset max offset unit fast corner slow corner c6 i7 a7 c6 c7 c8 i7 a7 input delay from pin to internal cells pad to i/o dataout to core 7 0 1.314 1.209 1.209 2.201 2.386 2.510 2.429 2.548 ns input delay from pin to input register pad to i/o input register 8 0 1.312 1.207 1.207 2.202 2.402 2.558 2.447 2.557 ns delay from output register to output pin i/o output register to pad 2 0 0.458 0.419 0.419 0.783 0.861 0.924 0.875 0.915 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.686 0.657 0.657 1.185 1.360 1.506 1.376 1.422 ns notes to table 1?43 : (1) the incremental values for the settings are generally linear. for the exact values fo r each setting, use the latest version of the quartus ii software. (2) the minimum and maximum offset timing numbers are in reference to setting 0 as available in the quartus ii software.
1?36 chapter 1: cyclone iv device datasheet switching characteristics cyclone iv device handbook, december 2013 altera corporation volume 3 table 1?44 and table 1?45 list the ioe programmable delay for cyclone iv gx devices. table 1?44. ioe programmable delay on column pins for cyclone iv gx devices (1) , (2) parameter paths affected number of settings min offset max offset unit fast corner slow corner c6 i7 c6 c7 c8 i7 input delay from pin to internal cells pad to i/o dataout to core 7 0 1.313 1.209 2.184 2.336 2.451 2.387 ns input delay from pin to input register pad to i/o input register 8 0 1.312 1.208 2.200 2.399 2.554 2.446 ns delay from output register to output pin i/o output register to pad 2 0 0.438 0.404 0.751 0.825 0.886 0.839 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.713 0.682 1.228 1.41 1.566 1.424 ns notes to table 1?44 : (1) the incremental values for the settings are generally linear. for exact values of each setting, use the latest version of th e quartus ii software. (2) the minimum and maximum offset timing numbers are in reference to setting 0 as available in the quartus ii software. table 1?45. ioe programmable delay on row pins for cyclone iv gx devices (1) , (2) parameter paths affected number of settings min offset max offset unit fast corner slow corner c6 i7 c6 c7 c8 i7 input delay from pin to internal cells pad to i/o dataout to core 7 0 1.314 1.210 2.209 2.398 2.526 2.443 ns input delay from pin to input register pad to i/o input register 8 0 1.313 1.208 2.205 2.406 2.563 2.450 ns delay from output register to output pin i/o output register to pad 2 0 0.461 0.421 0.789 0.869 0.933 0.884 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.712 0.682 1.225 1.407 1.562 1.421 ns notes to table 1?45 : (1) the incremental values for the settings are generally linear. for exact values of each setting, use the latest version of qu artus ii software. (2) the minimum and maximum offset timing numbers are in reference to setting 0 as available in the quartus ii software
chapter 1: cyclone iv device datasheet 1?37 i/o timing december 2013 altera corporation cyclone iv device handbook, volume 3 i/o timing use the following methods to determine i/o timing: the excel-based i/o timing the quartus ii timing analyzer the excel-based i/o timing provides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get a timing budget estimation as part of the link timing analysis. the quartus ii timing analyzer provides a more accurate and prec ise i/o timing data based on the specifics of the design after place-and-route is complete. f the excel-based i/o timing spreadsheet is downloadable from cyclone iv devices literature website. glossary table 1?46 lists the glossary for this chapter. table 1?46. glossary (part 1 of 5) letter term definitions a ?? b ?? c ?? d ?? e ?? f f hsclk high-speed i/o block: high-speed receiver/transmitter input and output clock frequency. g gclk input pin directly to global clock network. gclk pll input pin to global clock network through the pll. h hsiodr high-speed i/o block: maximum/minimum lvds data transfer rate (hsiodr = 1/tui). i input waveforms for the sstl differential i/o standard v il v ref v ih v swing
1?38 chapter 1: cyclone iv device datasheet glossary cyclone iv device handbook, december 2013 altera corporation volume 3 j jtag waveform k ?? l ?? m ?? n ?? o ?? p pll block the following highlights the pll specification parameters: q ?? table 1?46. glossary (part 2 of 5) letter term definitions tdo tck t jpzx t jpco t jsco t jsxz t jph t jsh t jpxz t jcp t jpsu_tms t jcl t jch tdi tms signal to b e capt u red signal to b e driven t jpsu_tdi t jszx t jssu core clock phase tap reconfigurable in user mode key clk n m pfd vco cp lf clkout pins gclk f i n pfd f i n f vco f out f out _ext switcho v er counters c0..c4
chapter 1: cyclone iv device datasheet 1?39 glossary december 2013 altera corporation cyclone iv device handbook, volume 3 r r l receiver differential input discrete resistor (external to cyclone iv devices). receiver input waveform receiver input waveform for lvds and lvpecl differential standards: receiver input skew margin (rskm) high-speed i/o block: the total margin left after accounting for the sampling window and tccs. rskm = (tui ? sw ? tccs) / 2. s single-ended voltage- referenced i/o standard the jedec standard for sstl and hstl i/o standards defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the receiver input crosses the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the dc threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing . sw (sampling window) high-speed i/o block: the period of time during which the data must be valid to capture it correctly. the setup and hold times determine the ideal strobe position in the sampling window. table 1?46. glossary (part 3 of 5) letter term definitions single-ended waveform differential waveform (mathematical function of positive & negative channel) positi v e channel (p) = v ih n egati v e channel (n) = v il ground v id v id 0 v v cm p - n v id v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss
1?40 chapter 1: cyclone iv device datasheet glossary cyclone iv device handbook, december 2013 altera corporation volume 3 t t c high-speed receiver and transmitter input and output clock period. channel-to- channel-skew (tccs) high-speed i/o block: the timing difference between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. t cin delay from the clock pad to the i/o input register. t co delay from the clock pad to the i/o output. t cout delay from the clock pad to the i/o output register. t duty high-speed i/o block: duty cycle on high-speed transmitter output clock. t fall signal high-to-low transition time (80?20%). t h input register hold time. timing unit interval (tui) high-speed i/o block: the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c /w). t injitter period jitter on the pll clock input. t outjitter_dedclk period jitter on the dedicated clock output driven by a pll. t outjitter_io period jitter on the general purpose i/o driven by a pll. t pllcin delay from the pll inclk pad to the i/o input register. t pllcout delay from the pll inclk pad to the i/o output register. transmitter output waveform transmitter output waveforms for the lvds, mini-lvds, ppds and rsds differential i/o standards: t rise signal low-to-high transition time (20?80%). t su input register setup time. u ?? table 1?46. glossary (part 4 of 5) letter term definitions single-ended waveform differential waveform (mathematical function of positive & negative channel) positi v e channel (p) = v oh n egati v e channel (n) = v ol ground v od v od v od 0 v v os p - n
chapter 1: cyclone iv device datasheet 1?41 glossary december 2013 altera corporation cyclone iv device handbook, volume 3 v v cm(dc) dc common mode input voltage. v dif(ac) ac differential input voltage: the minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage: the minimum dc input differential voltage required for switching. v icm input common mode voltage: the common mode of the differential signal at the receiver. v id input differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v ih voltage input high: the minimum positive voltage applied to the input that is accepted by the device as a logic high. v ih(ac) high-level ac input voltage. v ih(dc) high-level dc input voltage. v il voltage input low: the maximum positive voltage applied to the input that is accepted by the device as a logic low. v il (ac) low-level ac input voltage. v il (dc) low-level dc input voltage. v in dc input voltage. v ocm output common mode voltage: the common mode of the differential signal at the transmitter. v od output differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v od = v oh ? v ol . v oh voltage output high: the maximum positive voltage from an output that the device considers is accepted as the minimum positive high level. v ol voltage output low: the maximum positive voltage from an output that the device considers is accepted as the maximum positive low level. v os output offset voltage: v os = (v oh + v ol ) / 2. v ox (ac) ac differential output cross point voltage: the voltage at which the differential output signals must cross. v ref reference voltage for the sstl and hstl i/o standards. v ref (ac) ac input reference voltage for the sstl and hstl i/o standards. v ref(ac) = v ref(dc) + noise. the peak-to-peak ac noise on v ref must not exceed 2% of v ref(dc) . v ref (dc) dc input reference voltage for the sstl and hstl i/o standards. v swing (ac) ac differential input voltage: ac input differential voltage required for switching. for the sstl differential i/o standard, refer to input waveforms. v swing (dc) dc differential input voltage: dc input differential voltage required for switching. for the sstl differential i/o standard, refer to input waveforms. v tt termination voltage for the sstl and hstl i/o standards. v x (ac) ac differential input cross point voltage: the voltage at which the differential input signals must cross. w ?? x ?? y ?? z ?? table 1?46. glossary (part 5 of 5) letter term definitions
1?42 chapter 1: cyclone iv device datasheet document revision history cyclone iv device handbook, december 2013 altera corporation volume 3 document revision history table 1?47 lists the revision history for this chapter. table 1?47. document revision history date version changes december 2013 1.8 updated table 1?21 by adding note (15). may 2013 1.7 updated table 1?15 by adding note (4). october 2012 1.6 updated the maximum value for v i , v ccd_pll , v ccio , v cc_clkin , v cch_gxb , and v cca_gxb table 1?1. updated table 1?11 and table 1?22. updated table 1?21 to include peak-to-peak differential input voltage for the cyclone iv gx transceiver input reference clock. updated table 1?29 to include the typical dclk value. updated the minimum f hsclk value in table 1?31, table 1?32, table 1?33, table 1?34, and table 1?35. november 2011 1.5 updated ?maximum allowed overshoot or undershoot voltage?, ?operating conditions?, and ?pll specifications? sections. updated table 1?2, table 1?3, table 1?4, table 1?5, table 1?8, table 1?9, table 1?15, table 1?18, table 1?19, and table 1?21. updated figure 1?1. december 2010 1.4 updated for the quartus ii software version 10.1 release. updated table 1?21 and table 1?25. minor text edits. july 2010 1.3 updated for the quartus ii software version 10.0 release: updated table 1?3, table 1?4, table 1?21, table 1?25, table 1?28, table 1?30, table 1?40, table 1?41, table 1?42, table 1?43, table 1?44, and table 1?45. updated figure 1?2 and figure 1?3. removed sw requirement and tccs for cyclone iv devices tables. minor text edits. march 2010 1.2 updated to include automotive devices: updated the ?operating conditions? and ?pll specifications? sections. updated table 1?1, table 1?8, table 1?9, table 1?21, table 1?26, table 1?27, table 1?31, table 1?32, table 1?33, table 1?34, table 1?35, table 1?36, table 1?37, table 1?38, table 1?40, table 1?42, and table 1?43. added table 1?5 to include esd for cyclone iv devices gpios and hssi i/os. added table 1?44 and table 1?45 to include ioe programmable delay for cyclone iv e 1.2 v core voltage devices. minor text edits. february 2010 1.1 updated table 1?3 through table 1?44 to include information for cyclone iv e devices and cyclone iv gx devices for quartus ii software version 9.1 sp1 release. minor text edits. november 2009 1.0 initial release.

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